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PCB Capabilities

 

.
Attribute Standard Advanced Future
Minimum Outer Layer Line 0.004 0.003 0.002
Minimum Outer Layer Space 0.004 0.003 0.002
Minimum Inner Layer Line 0.004 0.003 0.002
Minimum Inner Layer Space 0.004 0.003 0.002
Minimum Outer Layer - Feature to Feature 0.005 0.004 0.003
Minimum Inner Layer - Feature to Feature 0.005 0.004 0.003
Minimum Space Conductor to Edge 0.025 0.02 0.015
Maximum Layer Count 30 40 50
Layer to layer Registration Tolerance +/- 0.005 +/- 0.004 +/- 0.003
Minimum Finished Thickness 0.02 0.01 0.008
Maximum Finished Thickness 0.24 0.3 0.35
Minimum Dielectric Thickness 0.0035 0.003 0.002
Minimum Impedance Tolerance -10% -7% -5%
Maximum Warp age Inch per inch 0.10% 0.70% 0.50%
Minimum Plated Hole Size - Finished 0.008 0.005 0.004
Hole Location Tolerance -0.004 -0.003 +/- 0.002
Maximum Aspect Ratio 8:01 10:01 14:01
Minimum Plane Relief over Drilled Hole 0.025 0.02 0.016
Minimum Inner Pad Size over Drilled Hole 0.012 0.01 0.008
Minimum Outer Pad Size over Drilled Hole 0.012 0.01 0.008
Plated Hole Tolerance -0.005 -0.003 +/- 0.001 - +/- 0.002
Minimum Solder Mask Web 0.005 0.004 0.003
Profiling Tolerances +/- 0.005 +/- 0.003 +/- 0.002
Minimum Feature Pitch - Grid Test 0.02 0.016 0.01
Minimum Feature Pitch - Flying Probe 0.015 0.01 0.008

 

Lead Time for PCB Prototype

Layers
Lead time(Natural Days which includes the weekends)
Minimum
Normal
2
1
5
4
2
5
6
3
7
8
3
7
10
5
10
12
6
10
14
8
10
16
8
10
18
8
10£¨11£©
20
10
14
22
10
14
24
10
14
26
10
14
28
10
14
30
10
14
Notes
The lead time may change based on diffirent technology requested and the board complexity.
 
 

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